View MB86961APD-G_3692770.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

de c ember 1999 d a t asheet mb86961a universal inter f a ce for 10 b ase -t 1 fe a tures ? full-dupl e x capability ? combines manchester encoder/decoder and twisted pair transce i v er functions ? direct interface to all popular ethernet controllers ? direct interface to a ui and 10 b ase-t outputs ? manual or automatic a ui /10 b ase-t selection ? int e grated pulse shaper and tx/rx ?lters ? selectable 10 0 w /15 0 w termination permits opera- tion with shielded or unshielded twisted pair cable ? r e v erse-polarity detection for rece i v er with auto- matic correction ? on-chip jabber logic, sqe test and link test with enable/disable option ? remote signaling of link d o wn and jabber condi- tions ? programmable rece i v e threshold for e xtended range ? output dr i v ers for rece i v e, transmit, collision and link test pass led indicators ? tp loopback enable/disable for e xternal loopback testing ? p o wer d o wn mode for minimum p o wer dissipation ? automatic shut-d o wn of unused port to reduce p o wer consumption ? l o w p o wer cmos technolog y , single 5 v olt p o wer supply ? 44-pin plcc and 48-pin pqfp packages general description the mb86961a un i v ersal interface for 10 b ase-t ( t wisted- p air) ethernet is fully compliant with the ieee 802.3 speci?cations for a ui (attachment unit interface) and 10 b ase-t ( t wisted- p air) interfaces and pr o vides the electrical interface between an ethernet controller and the db15 ( a ui) and rj45 (10 b ase-t) connections to an ethernet local area network. functions pr o vided by the mb86961a include manchester encoding and decoding of the serial data stream, l e v el co n v ersion, collision detec- tion, signal quality error (sqe) and link int e grity testing, jabber control, loopback, and automatic correction of polarity r e v ersal on the twisted-pair input. pulse shaping and ?ltering functions are performed by the mb86961a to eliminate the need for e xternal ?ltering components and thus reduce o v erall system cost. the d e vice also pr o vides outputs for rece i v e, transmit, colli- sion and link test leds and pr o vides compatibility with both shielded and unshielded twisted pair cables. the rece i v e threshold can be reduced to all o w an e xtended range between nodes in l o w noise e n vironments. its wide range of features and its ability to interface to virtually all popular controllers make the mb86961a the ideal d e vice for twisted pair ethernet applications. the mb86961a is part of a complete family of ethernet d e vices a v ailable from fujitsu. it is fabricated in a l o w- p o wer cmos technology and is supplied in a 44-pin plcc and 48-pin pqfp packages. pin configur a tion tpin tpip utp tponb tpona vcc2 gnd2 tpo p a tpopb plr r j ab 7 8 9 10 11 12 13 14 15 16 17 rld li j a b test tclk txd ten cl k o clki col a u t osel 39 38 37 36 35 34 33 32 31 30 29 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 18 t op view md1 nth cin vcc1 don dop dip paui din cip md0 ledr ledt/pdn ledl ledc/xlbk lbk gnd1 rbias rcmpt rxd cd rclk 4 0 4 1 4 2 4 3 4 4 1 2 3 4 5 6 (plcc p a c k age sh o wn)
mb86961a 2 pin pin pin pin pin assignment - 44-pin plcc 12 txd i 13 ten i 14 cl k o o 15 clki i 16 col o 17 a u t osel i 18 ledr o 19 ledt/pdn o/i 20 ledl o/i 21 ledc/xlbk o/i 22 lbk i 1 vcc1 2 cip i 3 cin i 4 nth i 5 md0 i 6 md1 i 7 rld o 8 l i i 9 j ab o 10 test i 11 tclk o 23 gnd1 24 rbias i 25 rcmpt o 26 rxd o 27 cd o 28 rclk o 29 r j ab o 30 plr o 31 tpopb o 32 tpo p a o 33 gnd2 34 vcc2 35 tpona o 36 tponb o 37 utp i 38 tpip i 39 tpin i 40 p a ui i 41 dip i 42 din i 43 dop o 44 don o ordering code p a ck a ge style p a ck a ge code v cc = +v + 5% lcc-44p-m02 mb86961apd- g 44-pin plastic leaded chip car r ier pin pin pin pin pin assignment - 48-pin pqfp 13 rld o 14 li i 15 j a b o 16 test i 17 tclk o 18 txd i 19 vcc 20 ten i 21 clk o o 22 clk i i 23 col o 24 a u t osel i 1 p a u i i 2 dip i 3 din i 4 dop o 5 don o 6 n c 7 vcc 8 cip i 9 cin i 10 nth i 11 md0 i 12 md1 i 25 ledr o 26 ledt/pdn o/i 27 ledl o/i 28 ledc/xlbk o/i 29 lbk i 30 gnd 31 nc 32 rbias i 33 rcmpt o 34 rxd o 35 cd o 36 rclk o 37 r j ab o 38 plr o 39 tpopb o 40 tpo p a o 41 gnd 42 vcc 43 vcc 44 tpona o 45 tponb o 46 utp i 47 tpip i 48 tpin i fp t -48p-m02 m b 86961apf- g 48-pin plastic quad flat p a c kage
3 mb86961a block diagram mode select logic controller compatibility/ port select/ polarity reverse/ loopback/link test manchester encoder remote signaling squelch/ link detect collision logic xtal osc manchester decoder pls only pls/mau select collision/ polarity/ detect/ correct rx slicer twisted pair interface pulse shaper & filter exl tx amp rx slicer drop cable interface collision receiver watch- dog timer pau i li lbk tclk clk1 ten txd rld rjab rcmpt cd ledl rxd rclk col md0 md1 utp tpopb tpopa tpona tponb tpip tpin dop don dip din cip cin do di ci ledt/pdn ledr ledc/xlbk nth jab plr cmos tx amp lpbk clk0
mb86961a 4 signal descriptions symbol type description autosel i automatic port select: when autosel=1, automatic port selection is enabled (the mb86981a defaults to the aui port only if tp link integrity=fail). when autosel=0, manual port selection is enabled (the paui pin determines the active port). cd o carrier detect: an output to notify the controller of activity on the network. cip cin i i aui collision pair: differential input pair connected to the aui transceiver ci cir- cuit. the input is collision signaling or sqe. clko clki o i crystal oscillator: a 20mhz crystal must be connected across these pins, or a 20 mhz clock applied at clki. col o collision detect: output which drives the collision detect input of the controller. dip din i i aui receive pair: differential input pair from the aui transceiver di circuit. the input is manchester encoded. dop don o o aui transmit pair: a differential output driver pair for the aui transceiver cable. the output is manchester encoded. jab o jabber indication: output goes high to indicate jabber state. lbk i loopback: when lbk=1, forced loopback is enabled. when lbk=0, normal loop- back is enabled. ledc/xlbk o/i collision led: open drain driver for the collision indicator. output is pulled low during collision ( half-duplex mode). if externally tied low, the mb86961a disables the internal tp loopback and collision detection circuits in anticipation of external tp loopback or full-duplex operation. mb86961a is ready for loopback testing 16 ms after this pin goes low. no delay is needed when the pin goes high. ledl o/i link led: open drain driver for link integrity indicator. output pulled low during link test pass. if externally tied low, internal circuitry is forced to link pass state and the mb86961a will continue to transmit link test pulses. ledr o receive led: open drain driver for the receive indicator led. output is pulled low during receive. ledt/ pdn o/i transmit led/power down: open drain driver for the transmit indicator. out- put is pulled low during transmit. if externally tied low, the mb86961a goes to power down state. li i link test enable: when li=0, the link integrity test function is disabled. when li=1, the link integrity test function is enabled. md0 md1 i i mode select: mode select pins which determine controller compatibility mode. see table 1. nth i normal threshold: when nth=1, the normal tp squelch threshold is in effect. when nth=0, the normal tp squelch threshold is reduced by 4.5 db. pau i i port/aui select: in manual port select mode (autosel=0), paui selects the active port. when paui=1, the aui port is selected, when paui=0, the tp port is selected. in auto port select mode, paui is ignored. plr o polarity reverse: output goes high to indicate reversed polarity. rbias i bias control: a bias resistor at this pin controls the bias of the operating circuit. rclk o receive clock: a recovered 10 mhz clock which is synchronous with the received data and connected to the controller receive clock input.
5 mb86961a signal descriptions (continued) symbol type description rcmpt o remote compatibility: output goes high to signal the controller that the remote port is compatible with the mb86961a remote signaling features. rjab o remote jabber: output goes high to signal the controller that the remote port is in jabber condition. rld o remote link down: output goes high to signal to the controller that the remote port is in link down condition. rxd o receive data: output signal connected directly to the receive data input of the controller. tclk o transmit clock: a 10 mhz clock output. this clock signal is directly connected to the transmit clock input of the controller. ten i transmit enable: enables data transmission and starts the watchdog timer. synchronous with tclk (see figures 14, 20, 26, and 32 for details). test i test: input for factory test of the device. leave open for normal operation. tpip tpin o o receive twisted-pair: a differential input pair from the twisted-pair cable. receive ?lter is integrated in-chip. no external ?lters are required. tpopa/b tpona/b o o transmit twisted pair: two differential driver pair outputs (a and b) to the twisted-pair cable. the output is pre-equalized, no external ?lter is required. two pairs are used to provide compatibility with both 100 w load cable and 150 w load cable. txd i transmit data: input signal containing nrz data to be transmitted on the net- work. txd is connected directly to the transmit data output of the controller. utp i utp/stp: when utp=0, 150 w termination for shielded tp is selected. when utp=1,100 w termination for unshielded tp is selected. vcc1, vcc2 power inputs: +5v power supply inputs. gnd1 gnd2 ground returns 1 & 2: grounds
mb86961a 6 applications figure 1 shows the mb86961a in a typical application, interfacing between a controller and the rj45 connector of the twisted-pair network. figures 2 through 5 show detailed diagrams of various mb86961a applications. auto port select loopback control pin with md0 and md1 both tied high, the mb86961a logic and framing are set to mode 4 (compatible with national ns8390 controllers). the autosel pin is tied high, allowing the mb86961a to automatically select the active port. the high at li enables link testing. the utp and nth pins are both tied high selecting the standard receiver threshold and 100 w termination for unshielded tp cable. (see figure 2.) manual port select link test function with md0 low and md1 tied high, the mb86961a logic and framing are set to mode 3 (compatible with fujitsus mb86960 controller). as in figure 3, the li pin is tied high, enabling link testing, and the utp and nth pins are both tied high, selecting the standard receiver thresh- old and 100 w termination for unshielded tp cable. how- ever, in this application autosel is tied low, allowing external port selection through the paui pin. the remote status output are inverted and used to drive led indica- tors. (see figure 3.) twisted-pair only figure 4 shows the mb86961a is a typical twisted-pair only application. the dte is connected to a 10base-t network through the twisted-pair rj45 connector. (the aui port is not used.) with md0 tied high and md1 grounded, the mb86961a logic and framing are set to mode 2 (compatible with intel 82586 controllers). the li pin externally controls the link test function. the utp and nth pins are both tied low, selecting the reduced receiver threshold and 150 w termination for shielded tp cable. the switch at ledt/pdn manually controls the power down mode. (see figure 4.) aui encoder/decoder only in this application, the dte is connected to the coaxial network through the aui. autosel and paui are both tied to ground, manually selecting the aui port. the twisted-pair port is not used. with md1 and md0 both grounded, the mb86961a logic and framing are set to mode 1 (compatible with amd am7990 controllers). the li pin is tied low, disabling the link test function. the lbk input controls loopback. a 20 mhz crystal con- nected across clki and clk0 provides the required clock signal. (see figure 5.) figure 1. typical system diagram mb86960 ethernet mb86961a 10base-t inter- 10base-t aui b u h o s
7 mb86961a figure 2. lan adapter boa r d application - a uto p o r t select with external loopba c k cont r ol ns8390 ba c k-end controller inter f ace loopba c k ena b le programming options remote status txd txe txc rxc rxd cps col +5 v 330 w line status + 1 m f t ant 0. 1 m f txd ten tclk rclk rxd cd col lbk p a u i a u t osel md0 md1 nth utp li riab rld rcmpt j a b plr ledc/xlbk ledr ledl ledt/pdn vcc1 vcc2 330 w 330 w 330 w clk1 20 pf 20 mhz clk0 20 pf 1 tpopb tpo p a tpona tponb tpip tpin cin cip don dop din dip rbias gnd1 gnd2 3 2 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 2 1 75 w 1% 37.5 w 1% 50 w 1% 12.4 k w 1% 78 w 1 : 2 1:1 18pf rj45 +12 v fuse t o 10base-t d-connector to a ui drop ca b le t wisted- p air net w o r k 78 w 78 w 50 w 1% 0.1 m f 37.5 w 1% 75 w 1% suita b le c r ystals includes: mt r on indust r ie s , inc. mp-1 and mp-2, and ecliptek ecsm20.000m suita b le tp trans f o r mers include: fil-mag 23z128 and sm23z128, v alor pt4069, and pulse enginee r ing pe-65745, pe-65454 and pe-68048 suita b le a ui trans f o r mers include: fil-mag 23z90 and sm23z90, and v alor l t6030 mb86961a
mb86961a 8 figure 3. lan adapter boa r d application - manual p o r t select with link t est function mb6950 or mb86960 ba c k-end controller inter f ace loopba c k ena b le programming options remote status txd ten tckn rckn rxd xcd -xcol +5 v 330 w line status + 1 m f t ant 0. 1 m f txd ten tclk rclk rxd cd col lbk p a u i a u t osel md0 md1 nth utp li riab rld rcmpt j a b plr ledc/xlbk ledr ledl ledt/pdn vcc1 vcc2 330 w 330 w 330 w clk1 20 pf 20 mhz clk0 20 pf 1 tpopb tpo p a tpona tponb tpip tpin cin cip don dop din dip rbias gnd1 gnd2 3 2 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 2 1 75 w 1% 37.5 w 1% 50 w 1% 12.4 k w 1% 78 w 1 : 2 1:1 18pf rj45 +12 v fuse t o 10base-t d-connector to a ui drop ca b le t wisted- p air net w o r k 78 w 78 w 50 w 1% 0.1 m f 37.5 w 1% 75 w 1% suita b le c r ystals include: mt r on indust r ie s , inc. mp-1 and mp-2, and ecliptek co r p . ecsm20.000m suita b le tp trans f o r mers include: fil-mag 23z128 and sm23z128, v alor pt4069, and pulse enginee r ing pe-65745, pe-65454 and pe-68048 suita b le a ui trans f o r mers include: fil-mag 23z90 and sm23z90, and v alor l t6030 330 w 330 w 330 w lbc mb86961a
9 mb86961a figure 4. t wisted- p air on l y application 82586 ba c k-end controller inter f ace loopba c k ena b le prog r amming options remote status txd - r td txc rxc rxd -crd -cdt +5 v 10k w line status + 1 m f t ant 0. 1 m f txd ten tclk rclk rxd cd col lbk p a u i a u t osel md0 md1 nth utp li riab rld rcmpt j a b plr ledc/xlbk ledr ledl ledt/pdn vcc1 vcc2 10k w 10k w clk1 20 pf 20 mhz clk0 20 pf 1 tpopb tpo p a tpona tponb tpip tpin rbias gnd1 gnd2 2 1 2 3 4 5 6 2 1 75 w 1% 37.5 w 1% 7 5 w 1% 12.4 k w 1% 1 : 2 1:1 18pf rj45 t o 10base-t t wisted- p air net w o r k 75 w 1% 0.1 m f 37.5 w 1% 75 w 1% suita b le c r ystals include: mt r on indust r ies inc. mp-1 and mp-2, and ecliptek co r p . ecsm20.000m suita b le tp trans f o r mers include: fil-mag 23z128 and sm23z128, v alor pt4069, and pulse enginee r ing pe-65745, pe-65454 and pe-68048 lbk cin cip don dop din dip p o wer d o wn ext. _bk mb86961a
mb86961a 10 figure 5. aui encoder/decoder only application ns8390 back-end controller interface loopback enable programming options remote status tx tena tclk rclk rx rena clsn +5 v 330 w line status + 1 m f tant 0.1 m f txd ten tclk rclk rxd cd col lbk pau i autosel md0 md1 nth utp li rjab rld rcmpt jab plr ledc/xlbk ledr ledl ledt/pdn vcc1 vcc2 330 w 330 w 330 w clk1 20 pf 20 mhz clk0 20 pf 1 tpopb tpopa tpona tponb tpip tpin cin cip don dop din dip rbias gnd1 gnd2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 12.4 k w 1% 78 w +12 v fuse d-connector to aui drop cable 78 w 78 w suitable crystals include: mtron industries inc. mp-1 and mp-2, and ecliptek corp. ecsm20.000m suitable aui transformers include: fil-mag 23z90 and sm23z90, and valor lt6030 mb86961a
11 mb86961a functional description the mb86961a universal ethernet interface transceiver performs the physical layer signaling (pls) and media attachment unit (mau) functions as de?ned by the ieee 802.3 speci?cation. it functions as a pls-only device (for use with 10base2 or 10base5 coaxial cable networks) or as an integrated pls/mau (for use with 10base-t twisted-pair networks). the mb86961a interfaces a back-end controller to either an aui drop cable or twisted-pair (tp) cable. the con- troller interface includes transmit and receive clock and nrz data channels, as well as mode control logic and signaling. the aui interface comprises three circuits: data output (do), data input (di) and collision (ci). the twisted-pair interface comprises two circuits: twisted-pair input (tpi) and twisted-pair output (tpo). in addition to the three basic interfaces, the mb86961a contains an internal crystal oscillator and four led driv- ers for visual status reporting. functions are de?ned from the back end controller side of the interface. the mb86961a transmit function refers to data transmitted by the back end to the aui cable (pls- only mode) or to the twisted-pair network (integrated pls/mau mode). the mb86961a receive function refers to data received by the back end from the aui cable (pls-only) or from the twisted-pair network (inte- grated pls/mau mode). in the integrated pls/mau mode, the mb86961a performs all required mau func- tions de?ned by the ieee 802.3 10base-t speci?cation such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. in the pls-only mode, the mb86961a receives incoming signals from the aui di circuit with up to 18ns of jitter and drives the aui do circuit. controller compatibility modes the mb86961a is compatible with most industry stan- dard controllers including devices produced by advanced micro devices (amd), intel, fujitsu and national semi- conductor. four different control signal timing and polar- ity schemes (modes 1 through 4) are required to achieve this compatibility. mode select pins md0 and md1 determine controller compatibility modes as listed in table 1. table 1. mb86961a compatibility modes ? mode 1: figures 12-17 ? mode 2: figures 18-23 ? mode 3: figures 24-29 ? mode 4: figures 30-35 the related timing speci?cations are provided in the elec- trical characteristics section of this data sheet. md1 md0 mode 0 0 mode 1: compatible with advanced micro devices am7990 con- trollers 0 1 mode 2: compatible with intel 82586 controllers 1 0 mode 3: compatible with fujitsus mb86960 controller 1 1 mode 4: compatible with national semiconductor 8390 control- lers
mb86961a 12 transmit function the mb86961a receives nrz data from the controller at the txd input (see mb86961a block diagram), and passes it through a manchester encoder. the encoded data is then transferred to either the aui cable (the do circuit) or the twisted-pair network (the tpo circuit). the advanced integrated pulse shaping and ?ltering network produces the output signal on tpon and tpop, shown in figure 6. the tpo output is pre-distorted and pre?ltered to meet the 10base-t jitter template. no external ?lters are required. during idle periods, the mb86961a trans- mits link integrity test pulses on the tpo circuit if li is enabled and integrated pls/mau mode is selected. the mb86961a can be programmed for either shielded tp (150 w ) or unshielded tp (100 w ) through the utp pin. jabber control function figure 7 is a state diagram of the mb86961a jabber con- trol function. the mb86961a on-chip watchdog timer prevents the dte from locking into a continuous transmit mode. when a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback func- tions, and activates the jab pin. once the mb86961a is in the jabber state, the txd circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jab- ber state. sqe function in the integrated pls/mau mode, the mb86961a sup- ports the signal quality error (sqe) function as shown in figure 8. after every successful transmission on the 10base-t network, the mb86961a transmits the sqe signal to the dte for 10 5 bit times over the internal ci circuit. receive function the mb86961a receive function acquires timing and data from the twisted-pair network (the tpi circuit) or from the aui (the di circuit). valid received signals are passed through the on-chip ?lters and manchester decoder and output as decoded nrz data and receive tim- ing on the rxd and rclk pins, respectively. no exter- nal ?lters are required. an internal intelligent squelch function discriminates noise from link test pulses and valid data streams. the receive function is activated only by valid data streams above the squelch level and with proper timing. if the dif- ferential signal at the tpi or the di circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the mb86961a receive function enters the idle state. if the polarity of the tpi circuit is reversed, the mb86961a detects the polarity reversal and reports it via the plr output. the mb86961a automatically cor- rects reversed polarity. polarity reverse function the mb86961a polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. a reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. reversed polarity is also detected if four frames are received with a reversed start-of-idle. whenever polarity is reversed, these two counters are reset to zero. if the mb86961a enters the link fail state and no valid figure 6. mb86961a tpo output waveform fi g ure 7. jabber control function xmit = disable lpbk = disable ci = sqe start_unjab_timer xmit = disable lpbk = disable ci = sqe unjab wait jab nonjabber output no output start_xmit_max_timer (do = active) (do = active)? (xmit_max_timer_done) (do = active) (unjab_timer_not_done) (do = idle) power on (unjab_timer_done) (do = idle)
13 mb86961a data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-?ipped condition. if link integrity testing is disabled, polarity detection is based only on received data. polarity correction is always enabled. collision detection function the collision detection function operates on the twisted- pair side of the interface. a collision is de?ned as the simultaneous presence of valid signals on both the tpi circuit and the tpo circuit. the mb86961a reports colli- sions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data is passed to the back-end over the rxd cir- cuit, disabling normal loopback. figure 9 is a state dia- gram of the mb86961a collision detection function. refer to electrical characteristics for collision detection and col/ci output timing. loopback function the mb86961a provides the normal loopback function speci?ed by the 10base-t standard for the twisted-pair port. the loopback function operates in conjunction with the transmit function. data transmitted by the back-end is internally looped back within the mb86961a from the txd pin through the manchester encoder/decoder to the rxd pin and returned to the back-end. the normal loopback function is disabled when a data collision occurs, clearing the rxd circuit for the tpi data. normal loopback is also disabled during link fail and jabber states. the mb86961a also provides additional loopback func- tions. an external loopback mode, useful for system-level testing, is controlled by pin 21 (ledc). when ledc is tied low, the mb86961a disables the collision detection and internal loopback circuits to allow external loopback or full-duplex operation. the mb86961a provides loop- back functions controlled by pin 22 (lbk). when the tp port is selected and lbk=1, tp loopback is forced, overriding collisions on the tp circuit. when lbk=0, normal loopback is in effect. figure 8. sqe function output detected output idle start_sqe_test_wait_timer (do = active) (do = idle) (sqe_test_wait_timer_done)? (xmit = enable) (xmit = disable) power on (sqe_test_timer_done) sqe test sqe wait test start_xmit_max_timer ci = sqe figure 9. collision detection function (do= active)? (tpi = active)? (xmit = enabled) (do= idle) (tpi = active) (do= active)? (tpi = idle)? (xmit = enabled) (do= active)? (tpi = idle) output tpo = do di = do idle collision tpo = do di = tpi input di = tpi ci = sqe (do= active)? (tpi = active)? (xmit = enabled) (do= idle) + (xmit = disabled) a a a (tpi = idle) power on
mb86961a 14 when the aui port is selected and lbk=1, data transmit- ted by the back-end controller is internally looped back from the txd pin through the manchester encoder/decod- er to the rxd pin. when lbk=0, no aui loopback occurs. link integrity test figure 10 is a state diagram of the mb86961a link integrity test function. the link integrity test is used to determine the status of the receive side twisted-pair cable. link integrity testing is enabled when pin 8 (li) is tied high. when enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traf?c. if no serial data stream or link integrity pulses are detected within 50-150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the mb86961a ignores any link integrity pulse with an interval less than 2-7 ms. the mb86961a will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. figure 10. link integrity test function link test fail extended start_link_test_min_timer start_link_test_max_timer xmit = disable link test fail start_link_test_min_timer start_link_test_max_timer xmit = disable rcvr = disable lpbk = disable link test fail reset link_count = 0 xmit = disable rcvr = disable lpbk= disable idle test start_link_loss_timer start_link_test_min_timer link test fail wait xmit = disable rcvr = disable lpbk= disable link_count = link count + 1 (tpi = active) ((link_test_rcvd = true) ? (link_test_min_timer_done)) (link_loss_timer_done) ? (tpi = idle) (link_test_rcvd = false) (tpi = idle ? link_test_max_timer_done) + ((link_test_min_timer_done) ? (link_test_rcvd = true)) (link_test_min_timer_done)? (link_test_rcvd = true) (link_test_rcvd = idle) ? (tpi = idle) (link_test_rcvd = false) ? (tpi = idle) (tpi = active) (tpi = idle) ? (tpi = active) + (link_count = lc_max) power on (do = idle)
15 mb86961a remote signaling the mb86961a transmits standard link pulses which meet the 10base-t speci?cation. however, the mb86961a encodes additional status information into the link pulse by varying the link pulse timing. this is referred to as remote signaling. using alternate pulse intervals, the mb86961a can signal three local condi- tions: link down, jabber, and remote signaling capability. figure 11 shows the interval variations used to signal local status to the other end of the line. the mb86961a also recognizes these alternate pulse intervals when received from a remote unit. remote status conditions are reported to the controller over the rld, rjab and rcmpt output pins. figure 11. remote signaling link integrity pulse timing 10ms 15ms 20ms 10ms 15ms 20ms 10ms 15ms 20ms 10ms 15ms 20ms 10ms 15ms 20ms 10ms 15ms 20ms 10ms 20ms 10ms 20ms 10ms 20ms 10ms 20ms li-rld 1 li-rjab 2 li-rcmpt 3 notes: 1. for remote link down (rld) signaling, the interval between li pulses increments from 10 ms to 15 ms to 20 ms, and then the cycle starts over. 2. for remote jabber (rjab) signaling, the interval between li pulses decrements from 20 ms to 15 ms to 10 ms, and then the cycle starts over. 3. for remote compatibility (rcmpt) signaling, the interval between li pulses continually switches between 10 ms and 20 ms.
mb86961a 16 electrical char a cteristics t a ble 2. absolute maximum r a tings note: exceeding these v alues may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for e xtended periods may a f fect d e vice reliabilit y . t a ble 3. input/output char a cteristics (t a = 0 c to +70 c, v cc = 5 v 5%) notes : 1 . t ypical ?gures are at 2 5 c and are for design aid only; not guaranteed and not subject to production testing. 2 . limited functional test patterns are performed at these input l e v els. the majority of functional tests are per- formed at l e v els 0v and 3 v . t a ble 4. a ui electrical char a cteristics (t a = 0 c to +70 c, v cc = 5 v 5%) note: t ypical ?gures are at 2 5 c and are for design aid only; not guaranteed and not subject to production testing. symbol rating conditions min. max. units v cc supply v oltage -0.3 6 v t op operating temperature 0 70 c t st storage temperature -65 150 c symbol p arameter condition min. t yp. 1 max. units v il input l o w v oltage 1 0.8 v v ih input high v oltage 2 2.0 v v ol output l o w v oltage i ol =3.2 ma 0.4 v i ol < 10 m a 10 %v cc v oh output high v oltage i oh = 4 0 m a 2.4 v i oh < 1 0 m a 90 %v cc icc supply current no r mal mode 90 ma p o w er-d o wn mode 5 ma t r output r ise time cmos tclk and rclk 3 ns ttl tclk and rclk 2 ns t f output f all time cmos tclk and rclk 3 ns ttl tclk and rclk 2 ns symbol p arameter condition min. t yp. 1 max. units i il input l o w current -700 m a i ih input high current 500 m a v od dif f erential output v oltage 550 1200 mv v ds dif f erential squelch threshold 220 mv
17 mb86961a table 5. tp electrical characteristics (t a = 0 c to +70 c, v cc = 5 v 5%) notes: 1. typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design, not subject to production testing. table 6. switching characteristics (t a = 0 c to +70 c, v cc = 5 v 5%) note: parameter is guaranteed by design; not subject to production testing. symbol parameter condition min. typ. 1 max. units z out transmit output impedance 5 w v od peak differential output voltage load=100 w at tpop and tpon 3.5 v t jit transmit timing jitter addition 0 line length 1 8 ns t jit transmit timing jitter addition after line model speci?ed by ieee 802.3 for 10base-t 3.5 ns z in receive input impedance between tpip/tpin, cip/cin and dip/din 20 k w v ds differential squelch threshold 420 mv v dsl lower squelch threshold 250 mv symbol parameter condition min. typ. max. units jabber timing t jab maximum transmit time 20 150 ms t ujab unjab time 250 750 ms link integrity timing t ll time link loss 55 66 ms t lp1 time between link integrity pulses 8 24 ms t lp2 interval for valid receive link integrity pulses 4.1 65 ms general t rst receive start-up delay 1 0 500 ns t tst transmit start-up delay 1 0 200 ns t lst loopback start-up delay 1 0 500 ns
mb86961a 18 table 7. rclk/start-of-packet timing note: typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 8. rclk/end-of-packet timing notes: 1. typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. cd turn off delay measured from middle of last bit, so timing speci?cation is unaffected by the value of the last bit. table 9. transmit timing note: typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 10. collision detection, col/ci output and loopback timing note: typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. symbol parameter min. typ. 1 max. units t data decoder acquisition time aui 900 ns tp 1300 ns t cd cd turn-on delay aui 50 ns tp 400 ns t rds receive data setup from rclk mode 1 40 ns modes 2, 3 and 4 30 ns t rdh receive data hold from rclk mode 1 10 ns modes 2, 3 and 4 30 ns symbol parameter type mode 1 mode 2 mode 3 mode 4 units t rch rclk hold after cd low min. 0 1 27 5 bt t rd rcv data throughput delay ty p. 300 275 275 275 ns t cdoff cd turn off delay ty p. 400 375 375 375 ns t ifg receive block out ty p. 2 50 27 5 bt symbol parameter min. typ. 1 max. units t ehch ten setup from tclk 30 ns t dsch txd setup from tclk 30 ns t chel ten hold after tclk 5 ns t chdu txd hold after tclk 5 ns symbol parameter min. typ. 1 max. units t cold col turn on delay 50 ns t coloff col turn off delay 160 ns t sqed sqe delay 0.65 1.6 m s t sqep sqe pulse duration 500 1500 ns t kheh lbk setup from ten 25 ns t khel lbk hold after ten 0 ns
19 mb86961a mode 1 (md1=0, md0=0) timing diagrams figures 12 - 17 tpip/tpin 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 cd t cd 1 0 1 0 1 0 1 0 1 1 1 rclk t rdh t rds 0 1 t data rxd note: rxd is triggered by the rising edge of rclk, with rclk advanced by 25 ns. the controller is sampled at the rising edge. figure 12. mode 1 rclk/sop timing figure 13. mode 1 rclk/eop timing tpip/tpin 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 cd rclk t rd t cdoff t ifg rxd
mb86961a 20 figure 14. mode 1 transmit timing ten tclk t ehch t chel txd t dsch t chdu figure 15. mode 1 collision detect timing ci col t cold t coloff figure 16. mode 1 col/ci output timing ten col t sqed t sqep figure 17. mode 1 loopback timing lbk ten t khel cd t kheh t caea
21 mb86961a mode 2 (md1=0, md0= 1 ) timing di a grams figures 18 - 23 figure 18. mode 2 rclk/sop timing figure 19. mode 2 rclk/eop timing note : rxd changes at the r ising edge of rclk. the controller is sampled at the f alling edg e . note : rxd changes at the r ising edge of rclk. the controller is sampled at the f alling edg e . tpip/tpin 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 cd t cd 1 0 1 0 1 0 1 0 1 1 1 rclk t rdh t rds 0 1 t d ata rxd tpip/tpin 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 cd rclk t rd t cdoff t ifg rxd
mb86961a 22 figure 20. mode 2 transmit timing ten tclk t ehch t chel txd t dsch t chdu figure 21. mode 2 collision detect timing ci col t cold t coloff figure 22. mode 2 col/ci output timing ten col t sqed t sqep figure 23. mode 2 loopback timing lbk ten t khel cd t kheh t caea t carrier detect blocked
23 mb86961a mode 3 (md1= 1 , md0=0) timing di a grams figures 24 - 29 figure 24. mode 3 rclk/sop timing tpip/tpin 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 cd t cd 1 0 1 0 1 0 1 0 1 1 1 rclk t rdh t rds 0 1 t d ata figure 25. mode 3 rclk/eop timing tpip/tpin 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 cd rclk t rd t cdoff t ifg rxd rxd note : rxd changes at the r ising edge of rclk. the controller is sampled at the f alling edg e . note : rxd changes at the r ising edge of rclk. the controller is sampled at the f alling edg e . 27 bits
mb86961a 24 figure 26. mode 3 transmit timing ten tclk t ehch t chel txd t dsch t chdu figure 27. mode 3 collision detect timing ci col t cold t coloff figure 28. mode 3 col/ci output timing ten col t sqed t sqep figure 29. mode 3 loopback timing lbk ten t khel cd t kheh t caea
25 mb86961a mode 4 (md1= 1 , md0= 1 ) timing di a grams figures 30 - 35 figure 30. mode 4 rclk/sop timing tpip/tpin 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 cd t cd 1 0 1 0 1 0 1 0 1 1 1 rclk t rdh t rds 0 1 t d ata figure 31. mode 4 rclk/eop timing tpip/tpin 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 cd rclk t rd t cdoff t ifg rxd rxd note : rxd changes at the f alling edge of rclk. the controller is sampled at the r ising edg e . note : rxd changes at the f alling edge of rclk. the controller is sampled at the r ising edg e .
mb86961a 26 figure 32. mode 4 transmit timing ten tclk t ehch t chel txd t dsch t chdu figure 33. mode 4 collision detect timing ci col t cold t coloff figure 34. mode 4 col/ci output timing ten col t sqed t sqep figure 35. mode 4 loopback timing lbk ten t khel cd t kheh t caea
27 mb86961a 18 28 29 17 7 6 1 44 40 39 17.53 0.13 sq 16.59 0.08 sq (.690 .005) (.653 .003) index details of a part r0.95(.037)typ 16.03 0.51 (.631 .020) r0.75(.030) typ 0.20 +0.05 -0.02 (.008 ) +.002 -.001 0.66(.026) typ 4.30 +0.22 -0.11 (.169 ) +.009 -.004 0.43(.017) typ 0.51(.020)min 0.10(.004) a 2.70 +0.60 -0.41 (.106 ) +.024 -.046 1.27 0.13 (050 .005) 16.03 0.51 (.631 .020) 12.70(.500)ref 44-pin plastic qfj (plcc) (lcc-44p-mo2) 44-pin plastic qfj (plcc) (case no.: lcc-44p-mo2) ? 1997 fujitsu limited c44052s-2c-4 dimension in mm (inches) no.: lead no. ordering information: MB86961APD-G
mb86961a 28 dimensions in inches (millimeters) 25 24 13 12 1 48 37 36 .006(0.16) m 48-lead plastic flat package (case no.: fpt-48p-m02) ? 1992 fujitsu limited f48002s-9c .006(0.15) .0315(0.80) .012 .002 a .002(0.05)min .346(8.80) .535 .016 .020(0.50) .006(0.15) .024(0.60) details of a part .006 +.002 (0.15 +0.05 .106(2.70)max .677 .016 sq .472 +.012 (12.0 +0.30 ) index lead no. .071 .012 details of b part b 0 to 10 ordering information: mb86961apf-g sq )
29 mb86961a lan-ds-20638-12/97 w orl d wide headqua r te r s japan fujitsu limited asia fujitsu mic r oelect r onics asia pte limited tel: fax: +81 44 754 3753 +81 44 754 3332 1015 kamiodanaka nakaharaku k a w asaki 211 j apan tel: fax: +65 281 0770 +65 281 0220 #05-08, 151 lorong chuan n e w t ech p ark singapore 556741 http://www.fujitsu.co.jp/ http://www.fsl.com.sg/ usa eu r ope tel: fax: +1 408 922 9000 +1 408 922 9179 fujitsu microelectronics inc 3545 no r th first street san jose ca 95134-1804 usa tel: fax: +49 6103 6900 +49 6103 69012 fujitsu mik r oelekt r onik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag ge r ma n y tel: fax: +1 800 866 8608 +1 408 922 9179 customer response center mon- f r i: 7am-5pm (pst) http://www.fujitsu.ede.com/ http://www.fujitsumicro.com/ all right reserved. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu microelectronics, inc. assumes no responsibility for inaccuracies. the information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu limited, its subsidiaries, or fujitsu microelectronics, inc. fujitsu microelectronics, inc. reserves the right to change products or specifications without notice. no part of the publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu microelectronics, inc.

▲Up To Search▲

Price & Availability of MB86961APD-G

	To Download MB86961APD-G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .